This invention relates generally to processes for fabricating integrated circuits, and more particularly to a technique that can be used in such processes to facilitate application of photoresist to a wafer without mottling preparatory to a masking and patterning procedure.
Conventional integrated circuit fabrication processes use one or more photolithographic steps to define patterns on the surface of a silicon wafer or similar substrate. These patterns are used in subsequent steps to form a wide variety of features which, together, form the active devices and interconnecting circuitry of an integrated circuit. As shown in FIG. 1, the substrate is ordinarly a semicircular wafer. A checkerboard pattern of square or rectangular dice is formed by scribe lines, along which the dice can be separated once the processing steps that are performed on the wafer have been completed.
Conventional photolithography comprises a number of well-known steps. First, the substrate is placed on a turntable. Then, the top substrate surface, upon which the circuit features are to be forced, is cleaned by a volatile liquid solvent. The solvent may include an appropriate bonding agent to assist in adhering a layer of photoresist, to be applied subsequently, to the substrate surface. Next, the turntable is operated to spin the wafer as indicated by the arrow in FIG. 1. This operation spins off the excess solvent and, conventionally, is continued until the substrate surface appears dry. Then the turntable is turned off. After the wafer ceases spinning, a predetermined quantity of liquid photoresist solution is dispensed onto the top substrate surface. The turntable is again operated to spin the wafer and thereby spread the liquid photoresist over the substrate surface. Once the photoresist layer is dried, it is selectively exposed, using either a mask or direct writing technique, to pattern each die in accordance with the desired configuration of one layer of the overall integrated circuit design layout. Subsequent steps, such as etching, doping, oxidation and various deposition steps, are performed using this and subsequently formed and patterned photoresist layers.
Many different factors can adversely affect the quality, uniformity and reliability of photolithographic techniques as used in state-of-the-art integrated circuit fabrication processes. These factors include the materials, techniques and conditions of application of the photoresist layer. Ideally, the resultant photoresist layer will be of such a quality that will enable accurate photoreproduction of all of the microscopic details of the mask, first, in the photoresist layer and, second, in the physical circuit features that are to be formed using this layer.
All of the physical, chemical and environmental factors need to be controlled carefully. Otherwise, a patterning step can fail, as to a wafer or an entire batch of wafers, or as to some proportion of the individual dice, dependent on the statistical effects of the fault-causing factor. Sometimes, individual factors alone may not be sufficient to cause problems but, in combination, will adversely affect the qualities of the photoresist layer and, ultimately, the quality of the resultant circuit structures.
The particular problem addressed by the present invention is to avoid mottling. Mottling is a defect in the distribution of a photoresist layer on a wafer in which portions of a substrate surface are not coated at all, or are inadequately coated by photoresist. The factors that lead to mottling are not well understood. Mottling seems to occur most commonly in photoresist layers that are applied over steep or undercut topographies, such as over-etched circuit layers, and on wafers in which the dies are rectangular rather than square. The affinity of a photoresist material for the exposed surface materials of the substrate is a factor. Silicon is phobic to many photoresist compositions, which is why bonding agents are used, although not with sure success. Another factor is the structure of the circuit itself. High density circuits, those having a high density of structural features formed on the top surface of the substrate, are more prone to problems than low density circuits.
Some levels of a given fabrication process are likely to be more sensitive than others. For example, applicant has worked extensively with Hewlett Packard's CMOSC process. Mottling problems have often occurred at the lateral channel stop (LCS) level. At this intermediate level, the surface structure includes substantial bare silicon and an etched nitride layer which presents an undercut lip to the photoresist. The occurrence of mottling was widely variable, and highly sensitive to minor changes of conditions or combinations of conditions. When all conditions were apparently optimal, mottling would affect as few a 1% of dice. When some conditions deteriorated, mottling would increase and commonly affect 30% of the dice, and on occasion entire lots of wafer have had to be reworked.
Prior attempts to discern and control the source of mottling have met with little success. One approach has been to simply flood the wafer surface with photoresist, using two or more times the usual amount of liquid photoresist. This met with little success and is wasteful of photoresist. It is also susceptible to problems, such as filter clogging, that affect the accurate metering of higher volumes of photoresist. It is also possible to allow the photoresist to stand on the substrate surface for an extended period of time before spinning off the excess, to give the photoresist time to fully wet the substrate surface. This approach can result in radially uneven distribution of the photoresist layer. Radially uneven photoresist distribution can interfere with close contact between the mask and the photoresist surface over the entire wafer, and uneven exposure of the photoresist layer, resulting in blurring of exposed boundaries in many dice.
Accordingly, a need remains for a technique for more reliably applying photoresist to wafers without mottling.